Electronic devices, such as tablets, computers, server, in-door telecom, out-door telecom, industrial computers, high performance computing data centers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components which leverage chip packages for increased functionality and higher component density. Conventional chip packages include one or more stacked components such as integrated circuit (IC) dies, through-silicon-via (TSV) interposer, and a package substrate, with the chip package itself stacked on a printed circuit board (PCB). The IC dies may include memory, logic, MEMS, RF or other IC device.
As the number and density of signal transmission routings, such as solder connections, through a vertical interface between any of these stacked components becomes greater, crosstalk between adjacent routings becomes increasingly problematic. The risk of increased crosstalk is also present stacked PCBs.
Conventional escape routing techniques utilized at the interface between chip package components and stacked PCBs generally employ multiple layers for vertically spacing horizontal routings. The thickness of the layers may be selected to reduce crosstalk potential. However, thick layers represent additional cost to the manufacturer, and do not improve crosstalk protection between vertical portions (i.e., vias) of the escape routing.
Therefore, a need exists for an improved vertical connection interfaces between stacked components of chip packages and PCBs that reduces crosstalk potential as compared what is conventionally utilized in the art.